Overview

The unit aims to develop a fundamental understanding of the performance, specification and fabrication of large scale digital circuits. You will become experienced at the design, simulation, verification and debugging of complex large scale digital circuits using a Hardware Description Language (HDL) and current CAD tools with FPGA development boards. … For more content click the Read More button below.

Rules

Enrolment Rule

Learning outcomes

On successful completion of this unit, you should be able to:
1.

Describe the fabrication processes used for producing CMOS VLSI circuits.

2.

Assess the performance of a VLSI layout in terms of speed, power and area.

3.

Predict and manage the metastable failure rate of crossing clock domains.

4.

Predict and optimise the delay in multiple paths of a VLSI design.

5.

Apply pipelining and parallelism to digital designs to improve their performance.

6.

Design, implement and debug a complex digital design using HDL as part of a team.

7.

Generate professional documentation for a team design project.

Assessment summary

Continuous assessment: 40%

Final assessment: 60%

This unit contains a hurdle requirement that you must achieve to be able to pass the unit. You are required to achieve at least 45% in the total continuous assessment component and at least 45% in the final assessment component. The consequence of not achieving a hurdle requirement is a fail grade (NH) and a maximum mark of 45 for the unit.

Workload requirements

Workload

Other unit costs

Costs are indicative and subject to change.