Overview
Requisites
Rules
Learning outcomes
Describe the fabrication processes used for producing CMOS VLSI circuits.
Assess the performance of a VLSI layout in terms of speed, power and area.
Predict and manage the metastable failure rate of crossing clock domains.
Predict and optimise the delay in multiple paths of a VLSI design.
Apply pipelining and parallelism to digital designs to improve their performance.
Design, implement and debug a complex digital design using HDL as part of a team.
Generate professional documentation for a team design project.
Assessment summary
Continuous assessment: 40%
Final assessment: 60%
This unit contains a hurdle requirement that you must achieve to be able to pass the unit. You are required to achieve at least 45% in the total continuous assessment component and at least 45% in the final assessment component. The consequence of not achieving a hurdle requirement is a fail grade (NH) and a maximum mark of 45 for the unit.
Workload requirements
Other unit costs
Costs are indicative and subject to change.
- Electronics, calculators and tools, at your own cost:
You are required to have a Faculty-approved scientific calculator - approximately $50