Overview
Offerings
Rules
Contacts
Chief Examiner(s)
Unit Coordinator(s)
Learning outcomes
Apply different techniques such as K-map and Quine McCluskey, to minimise logic expressions and implement them using primitive logical gates.
Analyse the operation of latches, flip-flops, multiplexors, decoders, counters, registers and use them in implementing complex digital systems.
Design and build complex digital systems using programmable logic devices such as PLAs, PALs and FPGAs.
Use a Hardware Description Language and Computer Aided Design Tools to synthesise and simulate logic circuits in a clear, consistent and efficient manner.
Analyse and design finite state sequential Mealy and Moore machines and implement them using different technologies.
Define time delays of digital logic elements and explain timing constraints necessary for correct operation of synchronous logic.
Teaching approach
Assessment summary
Continuous assessment: 40%
Final assessment: 60%
This unit contains hurdle requirements that you must achieve to be able to pass the unit. You are required to achieve at least 45% in the total continuous assessment component and at least 45% in the final assessment component. The consequence of not achieving a hurdle requirement is a fail grade (NH) and a maximum mark of 45 for the unit.
Assessment
Scheduled and non-scheduled teaching activities
Workload requirements
Learning resources
Other unit costs
Costs are indicative and subject to change.
- Electronics, calculators and tools, at your own cost:
You are required to have a Faculty-approved scientific calculator - approximately $50
Availability in areas of study
Electrical and computer systems engineering
Robotics and mechatronics engineering
Professional electrical engineering